1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to semiconductor memory devices having error correcting function.
2. Description of the Background Art
In many cases, an electrically programmable non-volatile memory, particularly EEPROM (Electrically Erasable and Programmable Read Only Memory) contains an error correcting circuit (referred to as ECC (Error Correcting Code) circuit hereinafter) for ensuring error free programming thereof more than ten thousand times. In the EEPROM, bit defects are generated because of deterioration of an oxide film with the number of programming increasing. An EEPROM is disclosed, for example, in U.S. Pat. No. 4,203,158. In such a memory, in case several bits become defective, the ECC circuit detects the defects and corrects the same to read correct data.
FIG. 8 is a block diagram showing a structure of a conventional semiconductor memory device containing an ECC circuit. In the semiconductor memory device of FIG. 8, a SEC (Single Error Correcting) code is used as an error correcting code. An error correcting code is described, for example, in R. W. Hamming, "Error Detecting and Error Correcting Codes", Bell Syst. Tech. J. 29, 147-160 (April 1950) and C. L. Chen and M. Y. Hsiao, "Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review", IBM J. RES. DEVELOP. 28, 124-134 (March 1984).
In FIG. 8, a memory array 1 comprises a plurality of memory cells arranged in a plurality of rows and columns. Each memory is comprised, for example, EEPROM cells. An address buffer 2 receives an externally applied address signal AD and applies the same to a row decoder 3 and a column decoder 4. The row decoder 3 selects one row in the memory array 1 in response to the address signal. The column decoder 4 selects a plurality of columns, for example 12 columns in the memory array 1 in response to the address signal. As a result, 12 memory cells are selected in the memory array 1.
In writing, data is written in the selected memory cells through a writing driver in a sense amplifier/writing driver 5. In reading, the data stored in the selected memory cells are amplified by the sense amplifier in the sense amplifier/writing driver 5 and outputted.
The semiconductor memory device contains an ECC circuit comprising an ECC encoder 7, an ECC decoder 8, a syndrome decoder 9 and a correction circuit 10. In the ECC circuit of FIG. 8, 4 bits of check bits are conventionally generated with respect to 8 bits (one byte) of the information bits.
Now reading operation and writing operation of the semiconductor memory device of FIG. 8 will be described.
First, in writing, 8 bits of data WD0-WD7 applied from the exterior is inputted in the ECC encoder 7 through an I/O buffer 6. The ECC encoder 7 generates 4 bits of check bits WDE0-WDE3 based on the inputted 8 bits of the data WD0-WD7. At the same time, the address signal is applied externally to the address buffer 2 and in response thereto 12 bits of memory cell are selected by the row decoder 3 and the column decoder 4. The above described 8 bits of the data WD0-WD7 and the 4 bits of the check bits WDE0-WDE3 are transferred to the sense amplifier/writing driver 5, and which bits are written into the selected memory cells in the memory array 1.
In reading, the 12 bits of data RD0-RD7 and RDE0-RDE3 stored in the memory cells selected by the row decoder 3 and the column decoder 4 are read out to be amplified in the sense amplifier/writing driver 5, and then applied to the ECC decoder 8.
The ECC decoder 8 generates 4 bits of syndromes S0-S3 based on the read out 12 bits of the data RD0-RD7 and RDE0-RDE3. Syndromes are described in H. Furutani et al., "A Built-In Hamming Code ECC Circuit for DRAM's", IEEE JOURNAL OF SOLID-STATE CIRCUITS, 24, 50-56 (February 1989) The syndrome decoder 9 decodes the syndromes S0-S3 to generate the 8 bits of the data SD0-SD7. When some of the data RD0-RD7 are erroneous, the corresponding bits in the 8 bits of the data SD0-SD7 are active. Therefore, the correction circuit 10 inverts bits in the read out data RD0-RD7 which correspond to the active bits in the 8 bit data SD0-SD7. Through the above described operation, the corrected data RDC0-RDC7 is externally outputted through the I/O buffer 6. If the number of the defective bits becomes above the correctable number, the chip becomes defective.
In the above described conventional semiconductor memory device even if several bits become defective, they are corrected by the ECC circuit, whereby correct data is externally read out. Therefore, it is not possible to foresee a chip which will be defective before hand to exchange the same to a new one before the chip becomes defective.
Therefore, proposed is a semiconductor memory device in which every time a defective bit is corrected by an ECC circuit, the number of the correction is counted by a counter. The application of the semiconductor memory device is filed on Oct. 15, 1988 as Japanese Patent Application No. 62-251930 (Counterpart U.S. application Ser. No. 253,001). However, in the semiconductor memory device, in order to grasp the number of defective bits in a chip, address signals corresponding to all the memory cells in the chip should be sequentially applied from the exterior. Thus, it is impossible with a simple operation to find deterioration state of the chip.
In addition, each time there is a need to find the number of defective bits to be corrected by the ECC circuit, such an operation as described above should be performed. Furthermore, even if the number of the defect bits to be corrected by the ECC circuit can be found, a user himself can not always use that information to identify a chip which can be expected to become defective. Besides, a user can not detect continuous defects and also can not predict the remaining life-time of a chip.